1. general description the 74aup1t98-q100 provides low-power, low-voltage configurable logic gate functions. eight patterns of 3-bit input determine the output state. the user can choose the logic functions mux, and, or, nand, nor, inverter and buffer. all inputs can be connected to v cc or gnd. this device ensures a very low static and dynamic power consumption across the entire v cc range from 2.3 v to 3.6 v. the 74aup1t98-q100 is designed for logic- level translation applications. the input switching levels accept 1.8 v low-voltage cmos signals, wh ile operating from either a single 2.5 v or 3.3 v supply voltage. the wide supply voltage range ensures normal operation as battery voltage drops from 3.6 v to 2.3 v. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventin g the damaging backflow current through the device when it is powered down. schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire v cc range. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 2.3 v to 3.6 v ? high noise immunity ? esd protection: ? mil-std-883, method 3015 class 3a. exceeds 5000 v ? hbm jesd22-a114f class 3a. exceeds 5000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? low static power consumption; i cc = 1.5 ? a (maximum) ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 3.6 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation 74aup1t98-q100 low-power configurable gate with voltage-level translator rev. 1 ? 19 may 2014 product data sheet
74aup1t98-q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rig hts reserved. product data sheet rev. 1 ? 19 may 2014 2 of 16 nxp semiconductors 74aup1t98-q100 low-power configurable gate with voltage-level translator 3. ordering information 4. marking 5. functional diagram 6. pinning information 6.1 pinning table 1. ordering information type number package temperature range name description version 74AUP1T98GW-Q100 ? 40 ? c to +125 ? c sc-88 plastic surface-mounted package; 6 leads sot363 table 2. marking type number marking code 74AUP1T98GW-Q100 ar fig 1. logic symbol d d g $ % & < fig 2. pin configuration sot363 $ 8 3 7 4 % & * 1 ' $ < d d d 9 & |